The present invention relates to a method of forming an insulating film in which a highly reliable oxide film can be formed at a low temperature and a method of fabricating a semiconductor device by utilizing the method of forming an insulating film.
In accordance with recent demands for high integration of semiconductor integrated circuits, for example, a very shallow junction structure is employed in forming a transistor and an STI (shallow trench isolation) structure is employed in forming an isolation. Since the very shallow junction structure and the STI are thus employed, dislocation defects are caused in an active region due to stress collected on the edge of the STI during formation of a gate oxide film (by thermal oxidation). As a result, junction leakage can be increased, or variation in the threshold voltage can be increased owing to change of junction profile caused in the formation of the gate oxide film. Therefore, in order to overcome these problems, it is very significant to conduct the process for forming an oxide film at a low temperature.
Also, in accordance with the demands for high integration of semiconductor integrated circuits, the gate length of a MOSFET is reduced, which makes it difficult to suppress the short channel effect. Therefore, the short channel effect is suppressed by employing a gate electrode structure designated as a dual gate electrode obtained by implanting phosphorus ions into a polysilicon film for a gate electrode of an NMOSFET and implanting boron ions into a polysilicon film for a gate electrode of a PMOSFET.
FIGS. 21(a) through 21(d) and 22(a) through 22(d) are sectional views for showing procedures in fabrication of a conventional CMOS device having a trench isolation structure and a dual gate electrode structure.
First, in the procedure shown in FIG. 21(a), a trench isolation region 101 is formed in a Si substrate 100, and then, a photoresist film 103 covering an NMOSFET formation region Rn and having an opening on a PMOSFET formation region Rp is formed on a protection oxide film 102 by photolithography. Thereafter, phosphorus ions (P+) for forming an N-type well region 104, phosphorus ions (P+) for controlling a threshold voltage and arsenic ions (As+) for stopping punch-through are implanted into a region of the Si substrate 100 within the opening of the photoresist film 103 (namely, the PMOSFET formation region Rp).
Then, in the procedure shown in FIG. 21(b), the photoresist film 103 is removed by ashing and RCA cleaning.
Next, in the procedure shown in FIG. 21(a), a photoresist film 105 covering the PMOSFET formation region Rp and having an opening on the NMOSFET formation region Rn is formed on the protection oxide film 102 by the photolithography. Thereafter, boron ions (B+) for forming a P-type well region 106, boron ions (B+) for controlling a threshold voltage and boron ions (B+) for stopping punch-through are implanted into a region of the Si substrate 100 within the opening of the photoresist film 105 (namely, the NMOSFET formation region Rn).
Then, in the procedure shown in FIG. 21(d), the photoresist film 105 is removed by the ashing and the RCA cleaning, and the protection oxide film 102 is also removed. Thereafter, the Si substrate 100 is heated at approximately 800 through 1000° C. in an oxygen atmosphere, thereby forming gate oxide films 107a and 107b on the N-type well region 104 and the P-type well region 106, respectively.
Subsequently, in the procedure shown in FIG. 22(a), after depositing a polysilicon film 108 for a gate electrode on the substrate, a photoresist film 109 covering the NMOSFET formation region Rn and having an opening on the PMOSFET formation region Rp is formed on the polysilicon film 108. Thereafter, boron ions (B+) are implanted into a region of the polysilicon film within the opening of the photoresist film 109 (namely, the PMOSFET formation region Rp).
Similarly, in the procedure shown in FIG. 22(b), after removing the photoresist film 109 by the ashing and the RCA cleaning, a photoresist film 110 covering the PMOSFET formation region Rp and having an opening on the NMOSFET formation region Rn is formed on the polysilicon film 108 by the photolithography. Thereafter, phosphorus ions (P+) are implanted into a region of the polysilicon film 108 within the opening of the photoresist film 110 (namely, the NMOSFET formation region Rn).
Next, in the procedure shown in FIG. 22(c), the photoresist film 110 is removed by the ashing and the RCA cleaning, and then, a heat treatment is carried out for activating the impurities implanted into the polysilicon film 108. In this manner, a P-type polysilicon film 108p is formed in the PMOSFET formation region Rp and an N-type polysilicon film 108n is formed in the NMOSFET formation region Rn.
Then, the P-type polysilicon film 108p and the N-type polysilicon film 108n are respectively patterned into a gate electrode 108a of the PMOSFET and a gate electrode 108b of the NMOSFET.
Furthermore, in order to cope with reduction in a chip area and high operation speed of a device, the resistance of the gate electrode of a MOSFET has recently been lowered. As one of promising means for lowering the resistance, the so-called polymetal gate structure or polycide gate structure in which part of the gate electrode is formed from a metal (refractory metal or its silicide) is known.
FIGS. 23(a) through 23(d) are sectional views for showing procedures in fabrication of a conventional CMOS device having the polymetal structure.
First, through the same procedures as those shown in FIGS. 21(a) through 21(d), a trench isolation region 101 for isolating a PMOSFET formation region Rp and an NMOSFET formation region Rn from each other, an N-type well region 104, a P-type well region 106 and gate oxide films 107a and 107b are formed in a Si substrate 100. Thereafter, as is shown in FIG. 23(a), a polysilicon film 120, a metal film 121 of titanium silicide or the like and an insulating film 122 of a silicon nitride film or the like are successively deposited on the substrate.
Next, in the procedure shown in FIG. 23(b), a photoresist film 115 covering a gate electrode formation region is formed by the photolithography, and then, dry etching (anisotropic etching) is carried out by using the photoresist film as a mask, thereby patterning the insulating film 122, the metal film 121 and the polysilicon film 120. In this manner, a gate electrode 125a including a bottom gate electrode 120a and a top gate electrode 121a, and an over-gate protection film 122a are formed in the PMOSFET formation region Rp. Also, a gate electrode 125b including a bottom gate electrode 120b and a top gate electrode 121b, and an over-gate protection film 122b are formed in the NMOSFET formation region Rn.
Then, in the procedure shown in FIG. 23(c), a photoresist film 116 covering the NMOSFET formation region Rn and having an opening on the PMOSFET formation region Rp is formed on the substrate. Thereafter, boron ions (B+) are implanted into the Si substrate 100 by using the photoresist film 116 and the gate electrode 125a as masks, thereby forming source/drain regions 126 of the PMOSFET.
Next, in the procedure shown in FIG. 23(d), the photoresist film 116 is removed by the ashing and the RCA cleaning, and then, a photoresist film (not shown) covering the PMOSFET formation region Rp and having an opening on the NMOSFET formation region Rn is formed on the substrate. Thereafter, arsenic ions (As+) are implanted into the Si substrate 100 by using the photoresist film and the gate electrode 125b as masks, thereby forming source/drain regions 127 of the NMOSFET. Then, the photoresist film is removed by the ashing and the RCA cleaning.
The conventional semiconductor devices fabricated as described above have, however, the following problems:
First, as is shown in FIG. 22(d), the gate oxide film 107a of the PMOSFET and the gate oxide film 107b of the NMOSFET have different thicknesses. This is because, in the thermal oxidation for forming the gate oxide films in the procedure of FIG. 21(d), the oxidizing rate is higher in the portion of the protection oxide film 102 corresponding to the NMOSFET formation region Rn where the boron ions are implanted than in the portion thereof corresponding to the PMOSFET formation region Rp where the phosphorus (or arsenic) ions are implanted. Also, since the impurity concentration profile in the P-type well region 106 for controlling the threshold voltage of the NMOSFET and the impurity concentration profile in the N-type well region 104 for controlling the threshold voltage of the PMOSFET are changed in the heat treatment conducted at 850 through 1000° C., the short channel effect of the MOSFETs are accelerated, variation in the threshold voltage of the NMOSFET and the PMOSFET is increased, and an off leakage current is increased.
Secondly, the boron implanted into the P-type polysilicon film 108p of the polysilicon film 108 for the gate electrode is diffused into the N-type well region 104 through the gate oxide film 107a due to the heat treatment conducted at 900 through 1000° C. for the thermal oxidation. As a result, the reliability of the gate oxide film is degraded, and variation in the threshold voltage of the PMOSFET is increased.
Thirdly, as is shown in FIG. 21(b), when the photoresist film 103 is removed by the ashing and the RCA cleaning after the ion implantation, the surface of the protection oxide film 102 becomes very rough. This is probably because the protection oxide film 102 is damaged by the ions during the ion implantation and is ununiformly etched by the RCA cleaning. When the ion implantation for forming the well region, namely, for controlling the threshold voltage, is carried out with the protection oxide film 102 having a very rough surface, the impurity concentration in a portion corresponding to a channel region within the well region is largely varied among MOSFETs. In this manner, variation in the threshold voltage among the MOSFETs is increased. Furthermore, the Si substrate 100 is also etched by the RCA cleaning. For example, when the RCA cleaning is carried out with the ion-implanted Si substrate exposed, a portion of the Si substrate 100 where the impurity ions have been implanted for controlling threshold voltage may also be etched by a thickness of several nm. As a result, the concentration profile of the implanted impurity is changed, so that the threshold voltage is largely varied in, particularly, a MOSFET having a buried transistor structure.
Fourthly, as is shown in FIG. 22(d), in patterning the polysilicon film 108 into the gate electrodes 108a and 108b, the surface of the active region of the Si substrate 100 can be roughened. Even when the etching end point of the polysilicon film is detected, the polysilicon film is not completely removed but partly remains as etching residues or sidewalls. Therefore, in order to remove the remaining portions of the polysilicon film, the polysilicon film is over-etched. Due to recent decrease in the thickness of a gate oxide film (to several nm), however, merely a portion of the gate oxide film not covered with the polysilicon film can be etched before completely removing the polysilicon film through the over-etching. Accordingly, when the Si substrate 100 below is partly etched, the surface of the active region is roughened. As a result, a good silicide layer cannot be formed in a salicidation process. Furthermore, the profile of the implanted ions for forming the source/drain regions cannot be uniform, resulting in increasing junction leakage.
Fifthly, as is shown in FIG. 23(d), in removing the photoresist film 116 by the ashing and the RCA cleaning after patterning the metal film 121, the top electrodes 121a and 121b, which are made from a metal in the gate electrodes 125a and 125b of the MOSFETS, are etched on their side faces. When metal ions dissolved in the etching solution (cleaning solution) enter the active region through the surface of the Si substrate 100, junction leakage is caused in the MOSFET. On the other hand, when a thermal oxide film for covering the substrate surface is formed to prevent this contamination, the top electrodes 121a and 121b formed from the metal are peeled.                Sixthly, as is shown in FIG. 22(b), in removing the photoresist films 109 and 110 by the ashing and the RCA cleaning or in conducting cleaning before loading the substrate in a furnace, the polysilicon film 108 is etched to some extent. Since the P-type polysilicon film 108p where the boron ions are implanted and the N-type polysilicon film 108n where the phosphorus (or arsenic) ions are implanted have different etch rates, there may be a step on the boundary between the P-type polysilicon film 108p and the N-type polysilicon film 108n. When this step is abrupt, although no problem can be observed in the sectional view shown in FIG. 22(d), the following problem may occur in a CMOS inverter having a silicide gate structure:                    FIGS. 24(a) through 24(c) are sectional views in a silicidation process for showing the gate electrodes 108a and 108b alone taken on line perpendicular to the section of FIG. 22(d) (namely, line XXIV—XXIV of FIG. 25). Furthermore, FIG. 25 is a plan view of the gate electrodes and a portion below the gate electrodes of the CMOS inverter. In this manner, in the CMOS inverter, the gate electrodes of the PMOSFET and the NMOSFET are mutually connected in the section perpendicular to the section of FIG. 22(d).                        
In the case where the abrupt step as shown in FIG. 24(a) is present, even when, for example, a Co film is deposited on the gate electrodes 108a and 108b for forming a silicide film on the gate electrodes 108a and 108b in a later procedure, the Co film cannot be sufficiently deposited on the side face of the step.
As a result, as is shown in FIG. 24(c), merely a very thin silicide film of CoSi2 or the like is formed or no silicide film is formed on the step through the silicidation. Accordingly, even when a voltage is applied to the gate electrode 108b of the NMOSFET in the CMOS inverter, the resistance between the gate electrodes can be too large to transfer the electric field to the gate electrode 108a of the PMOSFET.
Seventhly, the following problem occurs in forming the STI structure (trench isolation region). FIG. 26 is a sectional view for showing the shape of a conventional trench isolation region. As is shown in FIG. 26, a pad oxide film 131 and a masking nitride film 132 are stacked on a Si substrate 100, and a portion of the Si substrate 100 below an opening of the masking nitride film 132 is etched so as to form a trench 134. Then, a thermal oxide film 135 is formed by thermally oxidizing a portion of the Si substrate 100 within the trench, and the trench is filled with a CVD oxide film, so as to form a trench isolation region 136.
The thickness of the thermal oxide film 135 is, however, varied at respective edges within the trench depending upon the thickness of the masking nitride film 132, the thickness of the pad oxide film 131 or the plane size of the masking nitride film 132. In particular, when a hone phenomenon in which the thermal oxide film 135 has a small thickness at an edge is caused, an abrupt edge is formed at the corresponding corner of the Si substrate 100 within the trench 134. As a result, the electric filed is collected on the edge so as to cause problems such as breakdown of a gate insulating film and a hump characteristic (actuation of an edge transistor). The hone characteristic is conspicuous particularly when the thermal oxide film 135 is formed at a low temperature of 900° C. or less. Therefore, the temperature of the thermal oxidation can be set to 1000° C. for avoiding the hone phenomenon, but as the temperature of the thermal oxidation increases, larger stress is caused in the nitride film 132, resulting in increasing defects occurring in the Si substrate 100.